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MC68HC705RC16 — Rev. 3.0

General Release Specification

Parallel Input/Output (I/O)

General Release Specification — MC68HC705RC16

Section 7. Parallel Input/Output (I/O)

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.6

Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.2 Introduction

In user mode, 20 lines (28-pin PDIP or 28-pin SOIC) or 24 lines (44-lead

PLCC) are arranged as three 8-bit I/O ports. These ports are

programmable as either inputs or outputs under software control of the

data direction registers.

NOTE:

To avoid a glitch on the output pins, write data to the I/O port data

7.3 Port A

Port A is an 8-bit bidirectional port which does not share any of its pins

with other subsystems. The port A data register is at $0000 and the data

direction register (DDR) is at $0004. Reset does not affect the data

to inputs. Writing a one to a DDR bit sets the corresponding port bit to

output mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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