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HC705V8GRS/D Datasheet(PDF) 47 Page - NXP Semiconductors |
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HC705V8GRS/D Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 172 page  SECTION 5: INTERRUPTS Page 36 MC68HC705V8 Specification Rev. 2.1 Table 5-1. Vector Address for Interrupts and Reset The M68HC05 CPU does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tCYC secs An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 5-1 shows the sequence of events that occur during interrupt processing. Register N/A N/A N/A TSR MSR SPSR CTCSR Flag Name N/A N/A N/A OCF,ICF,TOF TXMS,RXMS SPIF TOFE,RTIE Interrupts Reset Software External Interrupts ** 16-bit Timer Interrupts MDLC Interrupt SPI Interrupt 8 bit Timer Interrupts CPU Interrupt RESET SWI IRQ TIMER MDLC SPI TIMER,RTI Vector Address $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9 $3FF6-$3FF7 $3FF4-$3FF5 $3FF2-$3FF3 ** External interrupts include IRQ, PORTA and PORTC sources. , Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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