HC805K3GRSSLASHD datasheet(57/119 Pages) NXP

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General Release Specification

Low-Power Modes

MC68HC805K3 — Rev. 1.0

Operational Modes

6.3.3 Wait Mode

The WAIT instruction places the MCU in a low-power wait mode, which

consumes more power than stop mode. In wait mode, the internal

processor clock is halted, suspending all processor and internal bus

activity. Internal timer clocks remain active, permitting interrupts to be

generated from the timer or a reset to be generated from the COP

watchdog timer. Execution of the WAIT instruction automatically clears

the I bit in the condition code register and sets the IRQE enable bit in the

IRQ status/control register so that the IRQ external interrupt is enabled.

All other registers, memory, and input/output lines remain in their

previous states.

If timer interrupts are enabled, a timer interrupt causes the processor to

exit wait mode and resume normal operation. Thus, the timer can be

used to generate a periodic exit from wait mode. Wait mode also is

exited when an external IRQ or RESET occurs.

6.3.4 COP Watchdog Timer Considerations

If the COP watchdog timer is enabled by the mask option register bit, any

execution of the STOP instruction (either intentional or inadvertent due

to the CPU being disturbed) causes the oscillator to halt and prevent the

COP watchdog timer from timing out unless the STOP instruction is

disabled by a mask option register bit.

If the mask option register bit is selected to enable the COP watchdog

timer, the COP resets the MCU when it times out. Therefore, it is

recommended that the mask option register bit be selected to disable the

COP watchdog for a system that must have intentional uses of the wait

mode for periods longer than the COP timeout period.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805K3GRS/D Datasheet(PDF) 57 Page - NXP Semiconductors