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STM32U545NET3QTR Datasheet(PDF) 219 Page - STMicroelectronics |
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STM32U545NET3QTR Datasheet(HTML) 219 Page - STMicroelectronics |
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219 / 283 page ![]() DS14216 Rev 1 219/283 STM32U545xx Electrical characteristics 258 The maximum value of RAIN can be found in the table below. IDDA_s(ADC) ADC consumption on VDDA Singe-ended mode fs = 2.5 Msps, resolution = 14 bits - 980 - µA fs = 1 Msps, resolution = 14 bits - 550 - fs = 10 ksps, resolution = 14 bits - 130 - fs = 2.5 Msps, resolution = 12 bits - 900 - fs = 2.5 Msps, resolution = 10 bits - 840 - fs = 2.5 Msps, resolution = 8bits - 770 - IDDV_s(ADC) ADC consumption on VREF+ Single-ended mode fs = 2.5 Msps, resolution = 14 bits - 160 - µA fs = 1 Msps, resolution = 14 bits -90 - fs = 10 ksps, resolution = 14 bits -15 - fs = 2.5 Msps, resolution = 12 bits - 150 - fs = 2.5 Msps, resolution = 10 bits - 150 - fs = 2.5 Msps, resolution = 8bits - 150 - 1. Specified by design. Not tested in production. 2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches). 3. Degraded differential linearity error below 10 MHz. 4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA. 5. The tolerance is 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. Table 103. 14-bit ADC1 characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit Table 104. Maximum RAIN for 14-bit ADC1(1)(2) (3) Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz 14 bits (2 LSB tolerance) 47 142 512 68 145 100 170 |
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