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STM32U535NET3QTR Datasheet(PDF) 212 Page - STMicroelectronics |
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STM32U535NET3QTR Datasheet(HTML) 212 Page - STMicroelectronics |
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212 / 278 page  Electrical characteristics STM32U535xx 212/278 DS14217 Rev 1 5.3.18 14-bit analog-to-digital converter (ADC1) characteristics Unless otherwise specified, the parameters given in the table below are values derived from tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage conditions summarized in Table 32. Note: It is recommended to perform a calibration after each power-up. Table 101. 14-bit ADC1 characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog power supply for ADC ON -1.62 - 3.6 V VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA VDDA < 2 V VDDA VREF- Negative reference voltage -VSSA fADC ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 5(3) -55 MHz ADC clock ratio - 45 - 55 % fs Sampling rate Resolution = 14 bits 0.23 - 2.5 Msps Resolution = 12 bits 0.25 - 2.75 Resolution = 10 bits 0.28 - 3.05 Resolution = 8 bits 0.31 - 3.44 tTRIG External trigger period Resolution = 14 bits 26 - - 1/fADC VAIN(4) Conversion voltage range -0 - VREF+ V VCIMV Common mode input voltage -VREF+/2 - 10% VREF+/2 VREF+/2 + 10% V RAIN(5) External input impedance Resolution = 14 bits Tj = 130 °C - - 1000 Ω Resolution = 12 bits Tj = 130 °C - - 1000 Resolution = 10 bits Tj = 130 °C - - 4700 Resolution = 8 bits Tj = 130 °C - - 22000 CADC Internal sample and hold capacitor -- 5 - pF tADCVREG_ STUP ADC LDO startup time - - - 17 µs tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle tCAL Offset and linearity calibration time - 25502 1/fADC tOFF_CAL Offset calibration time - 683 |
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