STM32U535NET3QTR datasheet(26/278 Pages) STMICROELECTRONICS

26 / 278 page

Functional overview

STM32U535xx

26/278

DS14217 Rev 1

3.5

Embedded SRAMs

Five SRAMs are embedded in the STM32U535xx devices, each with specific features.

SRAM1 and SRAM2 are the main SRAMs. SRAM4 is in the SRAM used for peripherals

LPBAM (low-power background autonomous mode) in Stop 2 mode.

These SRAMs are made of several blocks that can be powered down in Stop mode to

reduce consumption:

•

SRAM1: three 64-Kbyte blocks (total 192 Kbytes)

•

SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition

SRAM2 blocks can be retained in Standby mode.

•

SRAM4: 16 Kbytes

•

BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be

retained in all low-power modes and when VDD is off in VBAT mode, but not in

Shutdown mode.

3.5.1

SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset.

The SRAM1, SRAM2, and SRAM4 can be programmed as secure or nonsecure by blocks,

using the MPCBB (block-based memory protection controller).

The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions

can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone

security controller) in the GTZC (global TrustZone controller).

3.5.2

SRAMs privilege protection

The SRAM1, SRAM2, and SRAM4 can be programmed as privileged or unprivileged

by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page

of 512 bytes. Backup SRAM regions can be programmed as privileged or unprivileged

with watermark, using the TZSC (TrustZone security controller) in the GTZC (global

TrustZone controller).

3.6

TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU

(implementation defined attribution unit) define the access permissions based on secure

and nonsecure state.

•

SAU: up to eight SAU configurable regions are available for security attribution.

•

IDAU: It provides a first memory partition as nonsecure or nonsecure callable

attributes. It is then combined with the results from the SAU security attribution and

the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAM and peripheral

memory space is aliased twice for secure and nonsecure states. However, the external

memory space is not aliased.

STM32U535NET3QTR Datasheet(PDF) 26 Page - STMicroelectronics

STM32U535NET3QTR Datasheet(HTML) 26 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL