STM32U535NET3QTR datasheet(217/278 Pages) STMICROELECTRONICS

217 / 278 page

DS14217 Rev 1

217/278

STM32U535xx

Electrical characteristics

253

Figure 37. ADC accuracy characteristics

Figure 38. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function

1. Refer to the ADCx characteristic table for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance

(refer to Table 91: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the

conversion accuracy. To remedy this, fADC must be reduced.

3. Refer to Table 91: I/O static characteristics for the values of Ilkg.

4. Refer to Section 5.1.6: Power supply scheme.

General PCB design guidelines

The power-supply decoupling must be performed as shown in the corresponding

power-supply scheme. The 100 nF capacitor must be ceramic (good quality) and must be

placed as close as possible to the chip.

MSv19880V6

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End-point correlation line

n = ADC resolution

ET = total unadjusted error: maximum deviation

between the actual and ideal transfer curves

EO = offset error: maximum deviation between the first

actual transition and the first ideal one

EG = gain error: deviation between the last ideal

transition and the last actual one

ED = differential linearity error: maximum deviation

between actual steps and the ideal one

EL = integral linearity error: maximum deviation between

any actual transition and the end point correlation line

n-1

Output code

VSSA

n-2

n-3

VREF+ (VDDA)

1 LSB ideal

(1)

(2)

(3)

(or

)]

[1LSB =

VDDA

VREF+

MSv67871V3

Sample-and-hold ADC converter

Converter

Cparasitic

(2)

Ilkg

(3)

CADC

VDDA

(4)

RAIN

(1)

VAIN

RADC

VREF+

(4)

VSSA

I/O

analog

switch

Sampling

switch with

multiplexing

VSS

STM32U535NET3QTR Datasheet(PDF) 217 Page - STMicroelectronics

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