R31DS0118EU0101 Rev.1.01

Page 5

Apr 5, 2022

9QXL2000C Datasheet

6

^CKPWRGD_PD#

I, SE, PU,

PDT

Input notifies device to sample latched inputs and start up on first high assertion. Low

enters Power Down Mode, subsequent high assertions exit Power Down Mode. This

pin has internal pull-up resistor.

7

GNDR

GND

Analog ground pin for the differential input (receiver).

8

VDDR

PWR

Power supply for differential input clock (receiver). This VDD should be treated as an

analog power rail and filtered appropriately. Nominally 3.3V.

9

DIF_IN

I, DIF,

PDT

HCSL true input.

10

DIF_IN#

I, DIF,

PDT

HCSL complementary input.

11

^vSADR0_tri

I, SE, PD,

PU

SMBus address bit. This is a tri-level input that works in conjunction with other SADR

pins, if present, to decode SMBus Addresses. It has internal pull up/down resistors to

bias to VDD/2. See the SMBus Addressing table.

12

SMBDAT

I/O, SE,

OD, PDT

Data pin of SMBUS circuitry

13

SMBCLK

I, SE,

PDT

Clock pin of SMBUS circuitry

14

^vSADR1_tri

I, SE, PD,

PU

SMBus address bit. This is a tri-level input that works in conjunction with other SADR

pins, if present, to decode SMBus Addresses. It has internal pull up/down resistors to

bias to VDD/2. See the SMBus Addressing table.

15

NC

-

No connection.

16

NC

-

No connection.

17

DIF_19#

O, DIF

HCSL complementary clock output.

18

DIF_19

O, DIF

HCSL true clock output.

19

DIF_0

O, DIF

HCSL true clock output.

20

DIF_0#

O, DIF

HCSL complementary clock output.

21

VDD

PWR

Power supply, nominally 3.3V.

22

DIF_1

O, DIF

HCSL true clock output.

23

DIF_1#

O, DIF

HCSL complementary clock output.

24

DIF_2

O, DIF

HCSL true clock output.

25

DIF_2#

O, DIF

HCSL complementary clock output.

26

GND

GND

Ground pin.

27

DIF_3

O, DIF

HCSL true clock output.

28

DIF_3#

O, DIF

HCSL complementary clock output.

29

DIF_4

O, DIF

HCSL true clock output.

30

DIF_4#

O, DIF

HCSL complementary clock output.

31

VDD

PWR

Power supply, nominally 3.3V.

32

DIF_5

O, DIF

HCSL true clock output.

33

DIF_5#

O, DIF

HCSL complementary clock output.

34

OE5#

I, SE, PU,

PDT

Active low input for enabling output 5.

1 = disable output, 0 = enable output.

Pin

Number

Pin Name

Type

Description