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AX88871AP Datasheet(PDF) 18 Page - ASIX Electronics Corporation

Part # AX88871AP
Description  10/100BASE Dual Speed Bripeater Controller
PDF  30 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88871AP Datasheet(HTML) 18 Page - ASIX Electronics Corporation

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AX88871AP Bripeater
ASIX ELECTRONICS CORPORATION
18
The signals on the IR bus (such as IRD[3:0], IRD_V_N, IRD_ER_N, IRD_CK) flow either into or out of
the repeater depending upon the repeater‘s state. Only if the repeater receive packet from local port without
collision occurs, the IR signals flow out of repeater. Otherwise, these IR signals flow into repeater.
In cascade system, it must guarantee that only one repeater drives these signals to avoid contention.
3.7 RID Receive-Transmit Interface(Daisy Chain Logic)
In the cascade system, repeater ID of each chip will be re-arranged by serial in/serial out daisy chain
logic. The logic use DAISY_IN pin to monitor the RID value of the previous chained chip, and override the
original ID of the current chip with the value of (RID+1) . Use the DAISY_OUT pin to periodically (about
200us) send out the exact RID of the current chip to inform the next chained chip. By this way, each repeater
chip in 8 AX88871A stackable application will keep unique ID of itself. The RID is used in inter repeater bus
arbitration.
DAISY_IN/OUT frame format
idle
start bit
data0
data1
data2
data3
1
0
RID[0]
RID[1]
RID[2]
PARITY
Notes: PARITY = 1 when sum of 1‘s in RID[2:0] is even
If no daisy-chain input, that is, DAISY_IN keep high, the RID of current chip can be clear to 0 during
time out period. The timer for time out is about 4sec.
There are a input setting , /DIS_DAISY, which enable/disable daisy-chain function. With the low
setting , the RID of current chip don‘t care the present data on DAISY_IN and can‘t be overrided.
3.8 LED Display Interface
AX88871A provides per-port LED status indication for partition, jabber, activity and support rate -
based LED for global partition and collision, utilization (%) for 10/100Mbps. .Detail function is described on
the previous pin description(LED interface). LED[2:0] are all active low. There are two display ways :
complicated and simple way. It depends on the setting of MODE.
Multiple chips cascaded application (MODE = 1)
LED[2:0] Status Driver Wave-form as follows :
JAB7
JAB6
JAB5
JAB4
JAB3
JAB2
JAB1
JAB0
PART
7
PART
6
LED_CK
LED[0]
'0'
RID2
RID1
RID0
100M
GCOL
10M
GCOL
LED[1]
LED[2]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D12
D13
D14
D10
D15
PART
0
PART
1
PART
2
PART
3
PART
4
PART
5
ACT0
ACT1
ACT2
ACT3
ACT4
ACT5
ACT6
ACT7
10M
UTI7
10M
UTI0
10M
UTI1
10M
UTI2
10M
UTI3
10M
UTI4
10M
UTI5
10M
UTI6
100M
UTI7
100M
UTI0
100M
UTI2
100M
UTI3
100M
UTI4
100M
UTI5
100M
UTI6
100M
UTI1
G
PART
RAM
FAIL



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