P87C550EBAA datasheet(10/28 Pages) PHILIPS

10 / 28 page

Philips Semiconductors

Product specification

80C550/83C550/87C550

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer

1998 May 01

A/D CONVERTER PARAMETER DEFINITIONS

The following definitions are included to clarify some specifications

given and do not represent a complete set of A/D parameter

definitions.

Absolute Accuracy Error

Absolute accuracy error of a given output is the difference between

the theoretical analog input voltage to produce a given output and

the actual analog input voltage required to produce the same code.

Since the same output code is produced by a band of input voltages,

the “required input voltage” is defined as the midpoint of the band of

input voltage that will produce that code. Absolute accuracy error

not specified with a code is the maximum over all codes.

Nonlinearity

If a straight line is drawn between the end points of the actual

converter characteristics such that zero offset and full scale errors

are removed, then non-linearity is the maximum deviation of the

code transitions of the actual characteristics from that of the straight

line so constructed. This is also referred to as relative accuracy and

also integral non-linearity.

Differential Non-Linearity

Differential non-linearity is the maximum difference between the

actual and ideal code widths fo the converter. The code widths are

the differences expressed in LSB between the code transition

points, as the input voltage is varied through the range for the

complete set of codes.

Gain Error

Gain error is the deviation between the ideal and actual analog input

voltage required to cause the final code transition to a full-scale

output code after the offset error has been removed. This may

sometimes be referred to as full scale error.

Offset Error

Offset error is the difference between the actual input voltage that

causes the first code transition and the ideal value to cause the first

code transition. This ideal value is 1/2 LSB above Vref–.

Channel to Channel Matching

Channel to channel matching is the maximum difference between

the corresponding code transitions of the actual characteristics

taken from different channels under the same temperature, voltage

and frequency conditions.

Crosstalk

Crosstalk is the measured level of a signal at the output of the

converter resulting from a signal applied to one deselected channel.

Total Error

Maximum deviation of any step point from a line connecting the ideal

first transition point to the ideal last transition point.

Relative Accuracy

Relative accuracy error is the deviation of the ADC’s actual code

transition points from the ideal code transition points on a straight

line which connects the ideal first code transition point and the final

code transition point, after nullifying offset error and gain error. It is

generally expressed in LSBs or in percent of FSR.

WATCHDOG TIMER

The purpose of the watchdog timer is to reset the microcontroller

within a reasonable amount of time if it enters an erroneous state,

possibly due to a programming error, electrical noise, or RFI. When

enabled, the watchdog circuit will generate a system reset if the user

program fails to “feed” (or reload) the watchdog within a

predetermined amount of time.

The watchdog timer implemented on the 8XC550 has a

programmable interval and can thus be fine tuned to a particular

application. If the watchdog function is not used, the timer may still

be used as a versatile general purpose timer.

The watchdog function consists of a programmable 13-bit prescaler,

and an 8-bit main timer. The main timer is clocked by a tap taken

from one of the top 8 bits of the prescaler. The prescaler is

incremented once every machine cycle, or 1/12 of the oscillator

frequency. Thus, the main counter can be clocked as often as once

every 64 machine cycles or as seldom as once every 8192 machine

cycles.

When clocked, the main counter decrements. If the main watchdog

counter reaches zero, a system reset will occur. To prevent the

watchdog timer from under-flowing, the watchdog must be fed

before it counts down to zero. When the watchdog is fed, the

contents of the WDL register are loaded into the main watchdog

counter and the prescaler is cleared.

WDCON Register

MSB

LSB

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDMOD

Symbol

Position

Function

WDCON.7 PRE2

Prescaler select (read/write).

WDCON.6 PRE1

These bits select theprescaler divide ratio

WDCON.5 PRE0

according to the following table:

PRE2

PRE1

PRE0

DIVISOR (FROM fOSC)

× 64

× 64 × 2

× 64 × 4

× 64 × 8

× 64 × 16

× 64 × 32

× 64 × 64

× 64 × 128

WDCON.4

–

Not used

WDCON.3

–

Not used

WDCON.2 WDRUN Run control (read/write).

This bit turns the timer on (WDRUN = 1) or off

(WDRUN = 0) if the timer mode has been

selected.

WDCON.1 WDTOF Timeout flag (read/write).

This bit is set when the watchdog timer

underflows. It is cleared by an external reset

and can be cleared by software.

WDCON.0 WDMOD Mode selection (read/write).

When WDMOD = 1, the watchdog is selected;

when WDMOD = 0, the timer is selected.

Selecting the watchdog mode automatically

disables power-down mode. WDMOD is

cleared by external reset. Once the watchdog

mode is selected, this bit can only be cleared

by writing a 0 to this bit and then performing a

feed operation.

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