P87C550EBAA datasheet(14/28 Pages) PHILIPS

14 / 28 page

Philips Semiconductors

Product specification

80C550/83C550/87C550

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer

1998 May 01

DESIGN CONSIDERATIONS

At power-on, the voltage on VCC and RST must come up at the

same time for a proper start-up.

When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes control.

On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of

an unexpected write when idle is terminated by reset, the instruction

following the one that invokes idle should not be one that writes to a

port pin or to external memory. Table 2 shows the state of I/O ports

during low current operating modes.

Encryption Table

The encryption table is a feature of the 83C550 and 87C550 that

protects the code from being easily read by anyone other than the

programmer. The encryption table is 32 bytes of code that are

exclusive NORed with the program code data as it is read out. The

first byte is XNORed with the first location read, the second with the

second read, etc.

After the encryption table has been programmed, the user has to

know its contents in order to correctly decode the program code

data. The encryption table itself cannot be read out.

For the EPROM (87C550) part, the encryption table is programmed

in the same manner as the program memory, but using the “Pgm

Encryption Table” levels specified in Table 4. After the encryption

table is programmed, verification cycles will produce only encrypted

information.

For the ROM part (83C550) the encryption table information is

submitted with the ROM code as shown in Table 3.

Security Bits

There are two security bits on the 83C550 and 87C550 that, when

set, prevent the program data memory from being read out or

programmed further.

After the first security bit is programmed, the external MOVC

instruction is disabled, and for the 87C550, further programming of

the code memory or the encryption table is disabled. The other

security bit can of course still be programmed. With only security bit

one programmed, the memory can still be read out for program

verification. After the second security bit is programmed, it is no

longer possible to read out (verify) the program memory.

To program the security bits for the 87C550, repeat the

programming sequence using the “Pgm Security Bit” levels specified

in Table 4. For the masked ROM 83C550 the security bit information

is submitted with the ROM code as shown in Table 3.

ROM Code Submission

When submitting a ROM code for the 83C550, the following must be

specified:

1. The 4k byte user ROM program.

2. The 32 byte ROM encryption key.

3. The ROM security bits.

4. The watchdog timer parameters.

This information can be submitted in an EPROM (2764) or hex file

with the format specified in Table 3.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Table 3. ROM Code Submittal Requirements

ADDRESS

CONTENT

BIT(s)

COMMENT

0000H to 0FFFH

Data

7:0

User ROM data

1000H to 101FH

Key

7:0

ROM encryption key; FFH = no encryption

1020H

Security bit

ROM security bit 1

1020H

Security bit

ROM security bit 2

0 = enable security feature

1 = disable security feature

1030H

WDCON1

7:5

PRE2:0

1030H

WDCON1

Not used

1030H

WDCON1

Not used

1030H

WDCON1

WDRUN = 0, not ROM coded

1030H

WDCON1

WDTOF = 0, not ROM coded

1030H

WDCON1

WDMOD

1031H

Not used

1032H

7:0

Watchdog autoload value

(see specification)

NOTE:

1. See Watchdog Timer Specification for definition of WDL and WDCON bits.

P87C550EBAA Datasheet(PDF) 14 Page - NXP Semiconductors

P87C550EBAA Datasheet(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL