P87C550EBAA datasheet(12/28 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C550/83C550/87C550

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer

1998 May 01

Watchdog Function

The watchdog consists of a programmable prescaler and the main

timer. The prescaler derives its clock from the on-chip oscillator. The

prescaler consists of a divide by 12 followed by a 13 stage counter

with taps from stage 6 through stage 13. The tap selection is

programmable. The watchdog main counter is a down counter

clocked (decremented) each time the programmable prescaler

underflows. The watchdog generates an underflow signal (and is

autoloaded) when the watchdog is at count 0 and the clock to

decrement the watchdog occurs. The watchdog is 8 bits long and

the autoload value can range from 0 to FFH. (The autoload value of

0 is permissible since the prescaler is cleared upon autoload).

This leads to the following user design equations. Definitions: tOSC

is the oscillator period, N is the selected prescaler tap value, W is

the main counter autoload value, tMIN is the minimum watchdog

time-out value (when the autoload value is 0), tMAX is the maximum

time-out value (when the autoload value is FFH), tD is the design

time-out value.

tMIN = tOSC × 12 × 64

tMAX = tMIN × 128 × 256

tD = tMIN × 2PRESCALER × W

(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)

Note that the design procedure is anticipated to be as follows. A

tMAX will be chosen either from equipment or operation

considerations and will most likely be the next convenient value

higher than tD. (If the watchdog were inadvertently to start from FFH,

an overflow would be guaranteed, barring other anomalies, to occur

within tMAX). Then the value for the prescaler would be chosen from:

prescaler = log2 (tMAX / (tOSC × 12 × 256)) – 6

This then also fixes tMIN. An autoload value would then be chosen

from:

W = tD / tMIN – 1

The software must be written so that a feed operation takes place

every tD seconds from the last feed operation. Some tradeoffs may

need to be made. It is not advisable to include feed operations in

minor loops or in subroutines unless the feed operation is a specific

subroutine.

Interrupts

The 8XC550 interrupt structure is a seven-source, two-priority level

interrupt system similar to that of the standard 80C51

microcontroller. The interrupt sources are listed below in the order of

their internal polling sequence. This is the order in which

simultaneous interrupts of the same priority level would be serviced.

Interrupt Priorities

PRIORITY

SOURCE

VECTOR

ADDRESS

FUNCTION

Highest

INT0

0003H

External interrupt 0

TF0

000BH

Counter/timer 0 overflow

INT1

0013H

External interrupt 1

TF1

001BH

Counter/timer 1 overflow

TI & RI

0023H

Serial port transmit/receive

ADCI

002BH

A/D converter conversion

complete

Lowest

WDTOF

0033H

Watchdog timer overflow

(only when not in

watchdog mode)

Interrupt Control Registers

The standard 80C51 interrupt enable and priority registers have

been modified slightly to take into account the additional interrupt

sources of the 8XC550.

Interrupt Enable Register

MSB

LSB

EWD

EAD

ET1

EX1

ET0

EX0

Symbol Position

Function

IE.7

Global interrupt enable

EWD

IE.6

Watchdog timer overflow

EAD

IE.5

A/D conversion complete

IE.4

Serial port transmit or receive

ET1

IE.3

Timer 1 overflow

EX1

IE.2

External interrupt 1

ET0

IE.1

Timer 0 overflow

EX0

IE.0

External interrupt 0

Interrupt Priority Register

MSB

LSB

–

PWD

PAD

PT1

PX1

PT0

PX0

Symbol Position

Function

PWD

IP.6

Watchdog timer

PAD

IP.5

A/D conversion

IP.4

Serial port interrupt

PT1

IP.3

Timer 1 interrupt

PX1

IP.2

External interrupt 1

PT0

IP.1

Timer 0 interrupt

PX0

IP.0

External interrupt 0

Power-Down and Idle Modes

The 8XC550 includes the standard 80C51 power-down and idle

modes of reduced power consumption. In addition, the 8XC550

includes an option to separately turn off the serial port for extra

power savings when it is not needed. Also, the individual functional

blocks such as the counter/timers are automatically disabled when

they are not running. This actually turns off the clocks to the block in

question, resulting in additional power savings. Note that when the

watchdog timer is operating, the processor is inhibited from entering

the power-down mode. This is due to the fact that the oscillator is

stopped in the power-down mode, which would effectively turn off

the watchdog timer. In keeping with the purpose of the watchdog

timer, the processor is prevented from accidentally entering

power-down due to some erroneous operation.

Power Control Register

MSB

LSB

SMOD

SIDL

–

GF1

GF0

IDL

Symbol

Position

Function

SMOD

PCON.7

Double baud rate bit. When set to a 1 and

Timer 1 is used to generate baud rate, and

the serial port is used in modes 1, 2, or 3.

SIDL

PCON.6

Separately idles the serial port for additional

power savings.

–

PCON.5

Reserved

–

PCON.4

Reserved

GF1

PCON.3

General-purpose flag bit.

GF0

PCON.2

General-purpose flag bit.

PCON.1

Power-down bit. Starting this bit activates

power-down operation.

IDL

PCON.0

Idle mode bit. Setting this bit activates

idle mode operation.

If 1s are written to PD and IDL at the same time, PD takes

precedence.

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