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84330CVILF Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # 84330CVILF
Description  720MHz, Low Jitter, Crystal-to-LVPECL Frequency Synthesizer
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

84330CVILF Datasheet(HTML) 3 Page - Renesas Technology Corp

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©2016 Integrated Device Technology, Inc
Revision A January 13, 2016
84330CI Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Name
Type
Description
VCCA
Power
Analog supply pin.
XTAL1, XTAL2
Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output.
XTAL_SEL
Input
Pullup
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
OE
Input
Pullup
Output enable. LVCMOS / LVTTL interface levels.
nP_LOAD
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M0, M1, M2
M3, M4, M5
M6, M7, M8
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS /
LVTTL interface levels.
N0, N1
Input
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
VEE
Power
Negative supply pins.
TEST
Output
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
VCC
Power
Core supply pins.
nFOUT, FOUT
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
nc
Unused
No connect.
FREF_EXT
Input
Pulldown
PLL reference input. LVCMOS / LVTTL interface levels.
S_CLOCK
Input
Pulldown
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k



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