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DSP56600FM/AD Datasheet(PDF) 51 Page - NXP Semiconductors

Part # DSP56600FM/AD
Description  INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC
PDF  76 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56600FM/AD Datasheet(HTML) 51 Page - NXP Semiconductors

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Specifications
External Interface Module (EIM) Timing
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-9
EXTERNAL INTERFACE MODULE (EIM) TIMING
The EIM provides the bus interface between the DSP56651 and external memory and
peripherals. It uses the external address bus, data bus, bus control signals, and the
chip select signals.
Table 2-10
EIM External Bus Output AC Timing Specifications1
Num
Characteristics
MCU @16.8 MHz
Unit
Min
Max
11
MCU_CLK rise to address and R/W valid2
—4
ns
12
MCU_CLK rise to address and R/W invalid (output hold)
0
—
ns
13
MCU_CLK rise to CS asserted
—
4
ns
14
MCU_CLK rise to CS deasserted (output hold)
0
—
ns
15
MCU_CLK fall to OE, EB asserted (read, OEA = 0),
EB asserted (write)3
—4
ns
16
MCU_CLK rise to OE, EB asserted (read, OEA = 1)3
—4
ns
17
MCU_CLK rise to OE, EB deasserted (output hold) (read)3
0—
ns
MCU_CLK rise to EB deasserted (output hold) (write, WEN = 0)
0
—
ns
18
MCU_CLK fall to EB deasserted (output hold) (write, WEN = 1)
0
—
ns
19
MCU_CLK fall to OE, EB asserted (WSC = 0)3
—4
ns
20
MCU_CLK rise to OE, EB deasserted (output hold) (WSC = 0)3
0—
ns
21
Data-in valid to MCU_CLK rise (setup)
15
—
ns
22
MCU_CLK rise to data-in invalid (hold)
0
—
ns
23
MCU_CLK rise to data-out valid
—
4
ns
24
MCU_CLK rise to data-out invalid (output hold)
0
—
ns
25
MCU_CLK rise to data-out high impedance
—
4
ns
26
MCU_CLK fall to data-out valid (WSC = 0)
—
6
ns
27
MCU_CLK rise to data-out invalid (output hold) (WSC = 0)
0
—
ns
28
MCU_CLK rise to data-out high impedance (WSC = 0)
—
6
ns
Note:
1.
The following notes apply to this table:
•
Output timing is measured at the pin. The specifications assume a capacitive load of 50 pF.
•
R/W, EB, and CS deassertion to address change is 0 ns minimum.
•
MCU_CLK can be viewed on the CKO pin by programming the clock control register (CKCTL).
2.
Address setup to R/W and CS assertion is 0 ns minimum.
3.
EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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