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FS6407 Datasheet(PDF) 66 Page - NXP Semiconductors |
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FS6407 Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 111 page ![]() 66 NXP Semiconductors FS6407/FS6408 7.3 Detail of register mapping 7.3.1 Init VREG 1 7.3.2 Init Vreg 2 Table 17. INIT VREG1 register configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 0 0 1 P 0 0 0 0 0 0 0 Vcore_ FB MISO SPI_G WU CAN_G Reserve d IO_G Vpre_G Vcore_ G Vothers _G 0 Reserve d Reserve d Reserve d 0 0 Reserve d Vcore_F B Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserve d IO_G Vpre_G Vcore_ G Vothers _G 0 Reserve d Reserve d Reserve d 0 0 Reserve d Vcore_F B Table 18. Description and configuration of the bits (default value in bold) Vcore_FB Description Configure the monitoring of the second VCORE resistor string 0 No Monitoring (IO_1 is used as analog & digital input) 1 Monitoring enabled (IO_1 can NOT be used for analog/digital input neither for WU from LPOFF) Reset condition Power On Reset Table 19. INIT VREG2 register configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 0 1 0 P 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Vaux_tr k_EN 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ G Vothers _G 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Vaux_tr k_EN reserved Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ G Vothers _G 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Vaux_tr k_EN reserved |
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