IMXRT1040CEC datasheet(72/106 Pages) NXP

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4.9.4.1.4 MII serial management channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification.

However the ENET can function correctly with a maximum MDC frequency of 15 MHz.

Figure 47 shows MII asynchronous input timings. Table 65 describes the timing parameters (M10–M15) shown in the figure.

ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET_MDIO (input)

Figure 47. MII serial management channel timing diagram

Table 65. MII serial management channel timing

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

4.9.4.2 RMII mode timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET_RX_EN

is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET_TX_DATA[1:0],

ENET_RX_DATA[1:0] and ENET_RX_ER.

Figure 48 shows RMII mode timings. Table 66 describes the timing parameters (M16–M21) shown in the figure.

NXP Semiconductors

Electrical Characteristics

i.MX RT1040 Crossover Processors for Consumer Products, Rev. 2, 01/2023

Data Sheet: Technical Data

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