4

Functional Description

The Address Sequencer is a 24-bit programmable address

generator. As shown in the Block Diagram, the sequencer

consists of 4 functional blocks: the start circuitry, the

sequence generator, the crosspoint switch, and the proces-

sor interface. The addresses produced by the sequence

generator are input into the crosspoint switch. The cross-

point switch maps 24 bits of address input to a 24-bit output.

This allows for addressing schemes like “bit-reverse”

addressing for FFT’s. A programmable delay block is pro-

vided to allow the MSW of the output to be skewed from the

LSW. This feature may be used to compensate for proces-

sor pipeline delay when the sequence generator is config-

ured as two independent 12-bit sequencers. Address

Sequencer operation is controlled by values loaded into con-

figuration registers associated with the sequence generator,

crosspoint switch, and start circuitry. The configuration regis-

ters are loaded through the processor interface.

Start Circuitry

The Start Circuitry generates the internal START signal

which causes the Sequence Generator to initiate an

addressing sequence. The START signal is produced by

writing the Processor Interface’s “Sequencer Start” address

(see Processor Interface text), by asserting the STARTlN

input, or by the terminal address of a sequence generated

under “One-Shot Mode with Restart” (see Sequence Gener-

ator Section). Care should be taken to assert STARTlN for

only one clock cycle to ensure proper operation. A program-

mable delay from 1 to 31 clocks is provided to delay the initi-

ation of an addressing sequence by delaying the internal

START signal (see Processor Interface text).

The Start Circuitry generates the output signal ADDVAL

which is asserted when the first valid output address is at the

pads.

In

addition,

the

Start

Circuitry

generates

the

“STARTOUT” signal for multichip synchronization. Note:

STARTOUT

is

only

generated

when

an

addressing

sequence is started by writing the “Sequencer Start” address

of the Processor Interface, or an internal START is gener-

ated by reaching the end of an addressing sequence pro-

duced by “One-Shot Mode with Restart”.

Sequence Generator

The Sequence Generator is a block oriented address gener-

ator. This means that the desired address sequence is sub-

divided into one or more address blocks, each containing a

user defined number of addresses. User supplied configura-

tion data determines the number of address blocks and the

characteristics of the address sequence to be generated.

As shown in Figure 1, the Sequence Generator is subdivided

into the address generation and control sections. The

address generation section performs an accumulation based

on the output of MUX1 and MUX2. The control section gov-

erns the operation of the multiplexers, enables loading of the

Block Start Address register, and signals completion of an

address sequence.

An address sequence is started when the control section of

the Sequence Generator receives the internal START signal

from the Start Circuitry. When the START signal is received,

the control section multiplexes the contents of the Start

Address Register and a “0” to the adder. The result of this

summation is the first address in the first block of the

address sequence. This value is stored in the Block Start

Address register by an enable generated from the control

section, and the multiplexers are switched to feed the output

of the Holding and Address Increment registers to the adder.

Address generation will continue with the Address Increment

added to the contents of the Holding Register until the first

address block has been completed.

An address block is completed when the number of

addresses generated since the beginning of the address

block equals the value stored in the Block Size register.

When the last address of the block is generated, BLOCK-

DONE is asserted to signal the end of the address block

(see Application Note 9205). On the following CLK, the mul-

tiplexers are configured to pass the contents of the Block

Start Address and Block Increment registers to the adder

which generates the first address of the next address block.

An enable from the control section allows this value to

update the Block Start Address register, and the multiplexers

are switched to feed the Holding and Address Increment

registers to the adder for generation of the remaining

addresses in the block.

The address sequence is completed when the number of

address blocks generated equals the value loaded into the

Number of Blocks register. When the final address in the last

address block has been generated, DONE and BLOCK-

DONE are asserted to signal the completion of the address

sequence.

The parameters governing address generation are loaded

into five 24-bit configuration registers via the Processor

Interface. These parameters include the Start Address, the

beginning address of the sequence; the Block Size, the

number of addresses in the address block; the Address

Increment, the increment between addresses in a block; the

Number of Blocks, the number of address blocks in a

sequence (minimum 1); the Block Increment, the increment

between starting addresses of each block. The loading and

structure of these registers is detailed in the Processor Inter-

face text.

HSP45240