2

Pinouts

ADDRESS SEQUENCER HSP45240

68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)

Pin Descriptions

NAME

TYPE

PLCC

PIN

NUMBER

DESCRIPTION

VCC

I

6, 24, 34, 41

49, 55, 68

+5V power supply pin.

GND

I

3, 9, 18, 22,

38, 46, 52,

58, 65

GROUND.

RST

I

25

RESET: This active low input causes a chip reset which lasts for 26 clocks after RST

has been deasserted. The reset initializes the Crosspoint Switch and some of the con-

figuration registers as described in the Processor Interface Section. The chip must be

clocked for reset to complete.

CLK

I

23

CLOCK: The “CLK” signal is a CMOS input which provides the basic timing for address

generation.

WR

I

19

WRITE: The rising edge of this input latches the data/address on D0-6 to be latched into

the Processor Interface.

CS

I

21

CHIP SELECT: This active “low” input enables the configuration data/address on

D0-6 to be latched into the Processor Interface.

A0

I

20

ADDRESS 0: This input defines D0-6 as a configuration register address if “high”, and

configuration data if “low”, (see Processor Interface text).

D0-6

I

11-17

DATA BUS: Data bus for Processor Interface.

OEH

I

28

OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers

for OUT 12-23.

9 876543 2168 67 66 65 64 63 62 61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

NC

OUT12

GND

OUT11

OUT10

VCC

OUT9

OUT8

GND

OUT7

OUT6

VCC

OUT5

OUT4

GND

OUT3

NC

NC

D0

D1

D2

D3

D4

D5

D6

GND

WR

A0

CS

GND

CLK

VCC

RST

NC

HSP45240