12

AC Test Load Circuit

AC Electrical Specifications

VCC = 5.0V +5%, TA = 0°C to 70°C, (Note 7)

PARAMETER

SYMBOL

NOTES

-33 (33MHz)

-40 (40MHz)

-50 (50MHz)

UNITS

MIN

MIN

MIN

MAX

MIN

MAX

Clock Period

tCP

30

-

25

-

20

-

ns

Clock Pulse Width High

tCH

12

-

10

-

9

-

ns

Clock Pulse Width Low

tCL

12

-

10

-

9

-

ns

Setup Time D0-6 to WR High

tDS

14

-

13

-

12

-

ns

Hold Time D0-6 from WR High

tDH

0-0-0-

ns

Setup Time A0, CS, to WR Low

tAS

5-5-5-

ns

Hold Time A0, CS, from WR High

tAH

0-0-0-

ns

Pulse Width for WR Low

tWRL

13

-

12

-

10

-

ns

Pulse Width for WR High

tWRH

13

-

12

-

10

-

ns

WR Cycle Time

tWP

30

-

25

-

20

-

ns

Setup Time STARTIN, DLYBLK to Clock High

tIS

12

-

10

-

8

-

ns

Hold Time STARTIN, DLYBLK to Clock High

tIH

0-0-0-

ns

Clock to Output Prop., Delay on OUT0-23

tPDO

-15-13

-12ns

Clock to Output Prop. Delay on STARTOUT,

BLKDONE, DONE, ADDVAL and BUSY

tPDS

-15-13

-12ns

Output Enable Time

tEN

-20-15

-13ns

Output Disable Time

tOD

Note 6

-

20

-

15

-

13

ns

Output Rise/Fall Time

tORF

Note 6

-

5-3-

3ns

RST Low Time

tRST

2 Clock Cycles

ns

NOTES:

6. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or de-

sign changes.

7. AC Testing is performed as follows: Input levels (CLK input) = 4.0V and 0V; input levels (all other inputs) = 0V and 3.0V; input timing

reference levels: (CLK) = 2.0, Others) = 1.5V; Output timing references: VOH ≥ 1.5V, VOL ≤ 1.5V.

DUT

EQUIVALENT CIRCUIT

1.5V

IOL

IOH

S1

±

NOTES:

8. Includes stray and jig capacitance.

9. Switch S1 Open for ICCSB and ICCOP Tests.

OUTPUT PIN

CL

BLOCKDONE

DONE

ADDVAL

STARTOUT

BUSY

40pF

OUTTO-23

100pF

HSP45240