MPC93R51

REVISION 4 MARCH 14, 2016

6

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

APPLICATIONS INFORMATION

Programming the MPC93R51

The MPC93R51 clock driver outputs can be configured

into several divider modes. In addition, the external feedback

of the device allows for flexibility in establishing various input

to output frequency relationships. The output divider of the

four output groups allows the user to configure the outputs

into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even

dividers ensure that the output duty cycle is always 50%.

Table 7 illustrates the various output configurations. The

table describes the outputs using the input clock frequency

CLK as a reference.

The output division settings establish the output

relationship. In addition, it must be ensured that the VCO will

be stable given the frequency of the outputs desired. The

feedback frequency should be used to situate the VCO into a

frequency range in which the PLL will be stable. The design

of the PLL supports output frequencies from 25 MHz to

240 MHz while the VCO frequency range is specified from

200 MHz to 480 MHz and should not be exceeded for stable

operation.

Using the MPC93R51 in Zero-Delay Applications

Nested clock trees are typical applications for the

MPC93R51. For these applications the MPC93R51 offers a

differential LVPECL clock input pair as a PLL reference. This

allows for the use of differential LVPECL primary clock

distribution devices such as the Freescale MC100EP111 or

MC10EP222, taking advantage of its superior low-skew

performance. Clock trees using LVPECL for clock distribution

and the MPC93R51 as LVCMOS PLL fanout buffer with zero

insertion delay will show significantly lower clock skew than

clock distributions developed from CMOS fanout buffers.

The external feedback option of the MPC93R51 PLL

allows for its use as a zero delay buffer. The PLL aligns the

feedback clock output edge with the clock input reference

edge and virtually eliminates the propagation delay through

the device.

The remaining insertion delay (skew error) of the

MPC93R51 in zero-delay applications is measured between

the reference clock input and any output. This effective delay

consists of the static phase offset (SPO or t()), I/O jitter

(tJIT(), phase or long-term jitter), feedback path delay and

the output-to-output skew (tSK(O) relative to the feedback

output.

Table 7. Output Frequency Relationship(1) for an Example Configuration

1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.

Inputs

Outputs

FSELA

FSELB

FSELC

FSELD

QA

QB

QC

QD

0

0

0

0

2 * CLK

CLK

CLK

CLK

0

0

0

1

2 * CLK

CLK

CLK

CLK

 2

0

0

1

0

4 * CLK

2 * CLK

CLK

2* CLK

0

0

1

1

4 * CLK

2 * CLK

CLK

CLK

0

1

0

0

2 * CLK

CLK

 2

CLK

CLK

0

1

0

1

2 * CLK

CLK

 2

CLK

CLK

 2

0

1

1

0

4 * CLK

CLK

CLK

2 * CLK

0

1

1

1

4 * CLK

CLK

CLK

CLK

1

0

0

0

CLK

CLK

CLK

CLK

1

0

0

1

CLK

CLK

CLK

CLK

 2

1

0

1

0

2 * CLK

2 * CLK

CLK

2 * CLK

1

0

1

1

2 * CLK

2 * CLK

CLK

CLK

1

1

0

0

CLK

CLK

 2

CLK

CLK

1

1

0

1

CLK

CLK

 2

CLK

CLK

 2

1

1

1

0

2 * CLK

CLK

CLK

2 * CLK

1

1

1

1

2 * CLK

CLK

CLK

CLK