MPC93R51

REVISION 4 MARCH 14, 2016

11

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Figure 12. Propagation Delay (tPD, Static Phase

Offset) Test Reference

Figure 13. Propagation Delay (tPD) Test Reference

Figure 14. Output Duty Cycle (DC)

Figure 15. Output-to-Output Skew tSK(O)

VCC

VCC 2

GND

t()

PCLK

Ext_FB

PCLK

VCMR

VCMR

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device.

VCC

VCC 2

GND

VCC

VCC 2

GND

tSK(O)

VCC

VCC 2

GND

VCC

VCC 2

GND

t()

TCLK

Ext_FB

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage.

VCC

VCC 2

GND

tP

T0

DC = tP/T0 x 100%

Figure 16. Cycle-to-Cycle Jitter

Figure 18. I/O Jitter

Figure 19. Transition Time Test Reference

tF

tR

VCC=3.3 V

2.4

0.55

TJIT() = |T0–T1mean|

TCLK

(PCLK)

Ext_FB

The deviation in t0 for a controlled edge with respect to a t0 mean

in a random sample of cycles.

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs.

TN

TJIT(CC) = |TN–TN+1|

TN+1

The deviation in cycle time of a signal with respect to the ideal

period over a random sample of cycles.

TJIT(PER) = |TN–1/f0|

T0

Figure 17. Period Jitter