MPC93R51

REVISION 4 MARCH 14, 2016

7

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Figure 3. MPC93R51 Zero-Delay Configuration

(Feedback of QD4)

Calculation of Part-to-Part Skew

The MPC93R51 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs (TCLK or PCLK)

of two or more MPC93R51 are connected together, the

maximum overall timing uncertainty from the common TCLK

input to any output is:

tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() · CF

This maximum timing uncertainty consists of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter.

Figure 4. MPC93R51 Max. Device-to-Device Skew

Due to the statistical nature of I/O jitter, a RMS value (1

)

is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation, an

I/O jitter confidence factor of 99.7% (

 3) is assumed,

resulting in a worst case timing uncertainty from input to any

output of –251 ps to 351 ps relative to TCLK (VCC = 3.3 V and

fVCO = 400 MHz):

tSK(PP) = [-50ps...150ps] + [-150ps...150ps] +

[(17ps · –3)...(17ps ·3)] + tPD, LINE(FB)

tSK(PP) = [-251ps...351ps] + tPD, LINE(FB)

Above equation uses the maximum I/O jitter number

shown in the AC characteristic table for VCC = 3.3 V (17 ps

RMS). I/O jitter is frequency dependent with a maximum at

the lowest VCO frequency (200 MHz for the MPC93R51).

Applications using a higher VCO frequency exhibit less I/O

jitter than the AC characteristic limit. The I/O jitter

characteristics in Figure 5 can be used to derive a smaller

I/O jitter number at the specific VCO frequency, resulting in

tighter timing limits in zero-delay mode and for part-to-part

skew tSK(PP).

Figure 5. Max. I/O Jitter (RMS) Versus Frequency

for VCC = 3.3 V

Power Supply Filtering

The MPC93R51 is a mixed analog/digital product. Its

analog circuitry is naturally susceptible to random noise,

especially if this noise is seen on the power supply pins.

Noise on the VCCA (PLL) power supply impacts the device

characteristics, for instance, I/O jitter. The MPC93R51

provides separate power supplies for the output buffers (VCC)

and the phase-locked loop (VCCA) of the device. The purpose

of this design technique is to isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase-locked loop. In a digital system environment where it

is more difficult to minimize noise on the power supplies, a

Table 8. Confidence Factor CF

CF

Probability of clock edge within the distribution

MPC93R51

TCLK

QA

fref = 100 MHz

REF_SEL

PLL_EN

FSELA

FSELB

FSELC

FSELD

Ext_FB

QB

QC0

QC1

QD0

QD1

QD2

QD3

QD4

2 x 100 MHz

2 x 100 MHz

4 x 100 MHz

100 MHz (Feedback)

1

1

1

0

0

0

tPD,LINE(FB)

tJIT()

+tSK(O)

—t(

+t()

tJIT()

+tSK(O)

tSK(PP)

Max. skew

TCLKCommon

QFBDevice 1

Any QDevice 1

QFBDevice2

Any QDevice 2

 1

0.68268948

 2

0.95449988

 3

0.99730007

 4

0.99993663

 5

0.99999943

 6

0.99999999

Table 8. Confidence Factor CF

30

25

20

15

10

5

0

75

225

250

275

300

325

VCO frequency [MHz]

Max. I/O Jitter versus frequency

350

375

400