AD9980PCB datasheet(16/44 Pages) AD

16 / 44 page

AD9980

Preliminary Technical Data

Rev. 0 | Page 16 of 44

SOG INPUT

SOGOUT OUTPUT

CONNECTED TO

HSYNCIN

NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS

COMPOSITE

SYNC

AT HSYNCIN

VSYNCOUT

FROM SYNC

SEPARATOR

–300mV

700mV MAXIMUM

0mV

Figure 9. Sync Slicer and Sync Separator Output

Sync Separator

As part of sync processing, the sync separator’s task is to extract

Vsync from the composite sync signal. It works on the idea that

the Vsync signal stays active for a much longer time than the

Hsync signal. By using a digital low-pass filter and a digital

comparator, it rejects pulses with small durations (such as

Hsyncs and equalization pulses) and only passes pulses with

large durations, such as Vsync (see Figure 9).

The threshold of the digital comparator is programmable for

maximum flexibility. To program the threshold duration, write a

value (N) to Register 0x11. The resulting pulse width will be

N × 200 ns. So, if N = 5 the digital comparator threshold will be

1 µs. Any pulses less than 1 µs are rejected, while any pulse

greater than 1 µs passes through.

There are two things to keep in mind when using the sync

separator. First, the resulting clean Vsync output will be delayed

from the original Vsync by a duration equal to the digital

comparator threshold (N × 200 ns). Second, there is some

variability to the 200 ns multiplier value. The maximum varia-

bility over all operating conditions will be ±20% (160 ns to

240 ns). Since normal Vsync and Hsync pulse widths differ by a

factor of about 500 or more, the 20% variability is not an issue.

Hsync Filter and Regenerator

The Hsync filter is used to eliminate any extraneous pulses from

the Hsync or SOGIN inputs, outputting a clean, low-jitter signal

that is appropriate for mode detection and clock generation.

The Hsync regenerator is used to recreate a clean, although not

low jitter, Hsync signal that can be used for mode detection and

counting Hsyncs per Vsync. The Hsync regenerator has a high

degree of tolerance to extraneous and missing pulses on the

Hsync input, but is not appropriate for use by the PLL in

creating the pixel clock due to jitter.

The Hsync regenerator runs automatically and requires no

setup to operate. The Hsync filter requires the setting up of a

filter window. The filter window sets a periodic window of time

around the regenerated Hsync leading edge where valid Hsyncs

are allowed to occur. The general idea is that extraneous pulses

on the sync input will occur outside of this filter window and

thus will be filtered out. In order to set the filter window timing,

program a value (x) into Register 0x23. The resulting filter

window time is ±x times 25 ns around the regenerated Hsync

leading edge. Just as for the sync separator threshold multiplier,

allow a ±20% variance in the 25 ns multiplier to account for all

operating conditions (20 nS to 30 ns range).

A second output from the Hsync filter is a status bit (Reg-

ister 0x25, Bit 1) that tells whether extraneous pulses are present

on the incoming sync signal. Extraneous pulses are often

included for copy protection purposes; this status bit can be

used to detect that.

The filtered Hsync (rather than the raw Hsync/SOGIN signal)

for pixel clock generation by the PLL is controlled by Reg-

ister 0x20, Bit 2. The regenerated Hsync (rather than the raw

Hsync/ SOGIN signal) for the sync processing is controlled by

Hsync is recommended. See Figure 10 for an illustration of a

filtered Hsync.

AD9980PCB Datasheet(PDF) 16 Page - Analog Devices

AD9980PCB Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL