9.3 Power Supply Recommendations

The JFE150 is a JFET transistor with clamping diodes. There are no specific power-supply connections;

however, take care not to exceed any absolute maximum voltages on any of the pins if system supply voltages

greater than or equal to 40 V are used.

9.4 Layout

9.4.1 Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

• Reduce parasitic coupling by running the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Keep high impedance input signals away from noisy traces.

• Make sure supply voltages are adequately filtered.

• Minimize distance between source-connected and drain-connected components to the JFE150.

• Consider a driven, low-impedance guard ring around the critical gate traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

• Clean the PCB following board assembly for best performance.

• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture

introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at

85°C for 30 minutes is sufficient for most circumstances.

9.4.2 Layout Example

R

D

D

S

G

VCL

V

IN

V

DD

R

S

VCH

V

SS

V

DD

V

SS

C

S

Figure 9-9. JFE150 Layout Example, Common Source Configuration

JFE150

SLPS732B – JUNE 2021 – REVISED APRIL 2023

www.ti.com

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