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SLG51001 Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # SLG51001
Description  PMIC with High PSRR, Low Noise, Multi-Output LDOs and Integrated Load Switch
PDF  25 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SLG51001 Datasheet(HTML) 5 Page - Renesas Technology Corp

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SLG51001
PMIC with High PSRR, Low Noise, Multi-Output LDOs
and Integrated Load Switch
Datasheet
Revision 3.01
10-May-2022
CFR0011-120-00
5 of 25
© 2022 Renesas Electronics Corporation
Table 1: Pin Description
Pin No.
Pin Name
Type
(Table 2)
Drive
(mA)
Reset
State
Description
A2
CS
DI/PWR
Chip select. Also used as the OTP programming
power supply.
C1
GND
GND
Ground.
C2
GPI4_SCL
DI
1.2 V/1.8 V input cell, or I2C Serial Clock Line
(SCL).
B2
GPIO1
DIOD
1.2 V/1.8 V input cell, open-drain output.
B3
GPIO2
DIOD
1.2 V/1.8 V input cell, open-drain output.
C3
GPIO3_SDA
DIOD
1.2 V/1.8 V input cell, open-drain output, or I2C
Serial Data Line (SDA).
D2
VDD
PWR
Supply voltage for overall chip control. Controller
and power FET supply voltage for low noise
LDO (LDO1).
D3
VIN2_5
PWR
Controller and power FET supply voltage for
LDO2 and LDO5.
B4
VIN3_4
PWR
Controller and power FET supply voltage for
LDO3 and LDO4.
A1
VIN6
PWR
Controller and power FET supply voltage for
LDO6. LDO6 can be configured as a load switch
D1
VOUT1
PWR
LDO1 power output.
D4
VOUT2
PWR
LDO2 power output.
A4
VOUT3
PWR
LDO3 power output.
A3
VOUT4
PWR
LDO4 power output.
C4
VOUT5
PWR
LDO5 power output.
B1
VOUT6
PWR
LDO6 power output. LDO6 can be configured as
a load switch.
Table 2: Pin Type Definition
Pin Type
Description
Pin Type
Description
DI
Digital input
AI
Analog input
DO
Digital output
AO
Analog output
DIO
Digital input/output
AIO
Analog input/output
DIOD
Digital input/output open drain
BP
Back drive protection
PU
Pull-up resistor (fixed)
SPU
Switchable pull-up resistor
PD
Pull-down resistor (fixed)
SPD
Switchable pull-down resistor
PWR
Power
GND
Ground
2.1
Input Pins
2.1.1
CS
– Chip Select
This active-high pin is used to wake SLG51001 from a low-power reset state
To guarantee correct operation, CS must be de-asserted whenever the voltage at the VDD pin is out
of the operating conditions boundary (that is VDD < 2.8 V, or VDD > 5.0 V). See Guidelines for
Reliable Operation.



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