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SLG51001 Datasheet(PDF) 18 Page - Renesas Technology Corp |
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SLG51001 Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 25 page ![]() SLG51001 PMIC with High PSRR, Low Noise, Multi-Output LDOs and Integrated Load Switch Datasheet Revision 3.01 10-May-2022 CFR0011-120-00 18 of 25 © 2022 Renesas Electronics Corporation Parameter Description Conditions Min Typ Max Unit VOUT_STA TIC_LD Static load regulation Note 4 1 mA < IOUT < IOUT_MAX -8 2 mV VDROPOU T Dropout voltage @ VOUT = VOUT (VIN (Max)) - 10 mV IOUT = IOUT_MAX Note 5 100 Note 6 mV Dynamic Parameters VOUT_TR_ LINE Line transient response VIN = VOUT + VDROPOUT (Max) + 100 mV to VIN = VOUT + VDROPOUT (Max) VOUT = VOUT (Typ) IOUT = IOUT_MAX tR = tF = 100 mV/μs 2 5 mV VOUT_TR_ LD_1mA Load transient response VIN = VOUT + VDROPOUT (Max) VOUT = VOUT (Typ) IOUT = 1 mA to IOUT_MAX/2 tR = tF = 1 μs 21 29 mV tON Turn-on time Time to 90 % of VOUT IOUT = 0 mA C OUT = 20 μF 0.15 ms tOFF Turn-off time Time to 10 % of VOUT IOUT = 0 mA C OUT = 20 μF 2 5 Note 7 ms AC Parameters PSRR1kHz Power supply rejection ratio f = 1 kHz VIN = VOUT + VDROPOUT (Max) + 200 mV VOUT = VOUT (Typ) IOUT = IOUT_MAX/2 COUT = 20 μF 76 dB PSRR100k Hz Power supply rejection ratio f = 100 kHz VIN = VOUT + VDROPOUT (Max) + 200 mV VOUT = VOUT (Typ) IOUT = IOUT_MAX/2 COUT = 20 μF 54 dB VN Output noise f = 10 Hz to 100 kHz IOUT = IOUT_MAX/2 100 μV |
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