ZAMC4100GA2R datasheet(72/156 Pages) RENESAS

72 / 156 page

ZAMC4100 Datasheet

January 26, 2016

Figure 3.18 Effect of Driver Enable When the PWM is Running

HS3PWMEN

PWM signal

HS3

HS3EN

START

STOP

3.10.5. PWM Module in SLEEP and STANDBY Mode

When SLEEP or STANDBY Mode is activated, the PWM signal generation is automatically disabled by clearing

the value of register PWMDCFG (i.e., zero the duty-cycle). The drivers’ PWM enable bits in register PWMDREN

are also cleared. If needed after wake-up, the MCU can reinitialize the PWM unit following the procedure

explained in the previous section.

As a recommended practice, before entering the SLEEP or STANDBY Mode, the MCU should stop the PWM in

order to ensure that the drivers will not be disabled during the PWM pulse generation phase; i.e. no glitches at the

drivers’ outputs.

3.11. EC Mirror Driver

The structure of the EC mirror (ECM) driver is shown in Figure 3.19. It is controlled via register ECMCTRL (see

Table 3.27). Setting the ECMEN bit in this register enables the driver while the output voltage is controlled by a 6-

bit DAC programmed by the ECMDAC bits.

The driver operates as the DAC voltage is continuously compared with the voltage measured at the EC_M pin by

the error amplifier. Depending on the comparison result, it controls both transistors of the output stage to provide

a current with a direction and value necessary for achieving the desired voltage across the electrochromatic

mirror terminals. The reflectivity of the mirror is controlled precisely with respect to the desired level (set by bits

ECMDAC[5:0] in the ECMCTRL register).

In order to limit the current through the load and to reduce the power dissipation of the driver inside the chip, an

external resistor is connected in series between the high-side transistor of the output stage and the EC mirror. It

must withstand power in the range of 0.5W to 1W depending on the nominal supply voltage, the static current

consumption, and the expected dynamic current consumption.

For achieving maximum reflectivity of the mirror in the fastest possible way, it is necessary that the voltage across

the electrochromatic material (CECM) to be reduced to zero. This is achieved by completely turning on the low-side

transistor of the output stage of the ECM driver, which shorts the terminals of the mirror and provides a low

resistance current path for discharging. If the equivalent resistance of that switch is low (see Table 1.9), the time

necessary for that transition is determined mainly by the parameters of the EC mirror (CECM, RECMs, RECMp) and the

initial voltage to which it has been charged. This feature is enabled by the dedicated bit DSCEN in the ECMCTRL

Like all other power drivers in the ZAMC4100, the ECM driver is automatically disabled in the event of an

over/under voltage event or overheating of the system.

ZAMC4100GA2R Datasheet(PDF) 72 Page - Renesas Technology Corp