ZAMC4100GA2R datasheet(24/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

1.3.3.

SPI Bus Timing

Refer to Figure 1.2 and Table 1.16 for the definitions of the SPI timing parameters.

Table 1.16 ZAMC4100 SPI Bus Timing Parameters

Parameter

Symbol

Min.

Typ.

Max.

Unit

SPI clock period

tCLK

0.3

6.4

µs

SPI pulse width

40% tCLK

50% tCLK

60% tCLK

µs

Chip-select setup time

tCSNSU

1.0

µs

Chip-select hold time

tCSNHD

1.0

µs

SPI access time

tACC

1.0

2.0

µs

The maximum tCLK value is determined by the maximum value that can be programmed in MCU register Z1_SPICLKCFG[7:2] (see Table 4.23).

The parameters tCSNSU and tCSNHD require at least 3 OSCH clock cycles. When oscillator OSCH is not trimmed, it runs at a lower frequency.

Figure 1.2 SPI Communication Timing Diagram

MOSI

SPI_CLK

MISO

tCSNSU

tCSNHD

tACC

tCLK

CMD/SSB

R/W DATA

CSN

ZAMC4100GA2R Datasheet(PDF) 24 Page - Renesas Technology Corp

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