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PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

1.8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the 604e.

1.8.1 PLL Configuration

The 604e PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the

604e is shown in Table 11 for nominal frequencies.

Table 11. PowerPC 604e Microprocessor PLL Configuration

PLL_CFG[0–3]

CPU Frequency in MHz (VCO Frequency in MHz)

CPU/

SYSCLK

Ratio

VCO

Multiplier

Bus

25

MHz

Bus

33.3

MHz

Bus

40

MHz

Bus

50

MHz

Bus

60

MHz

Bus

66.6

MHz

Bus

75

MHz

1100

1.5:1

x2

—

—

—

—

—

100

(200)

112.5

(225)

0100

2:1

x2

—

—

—

100

(200)

120

(240)

133

(267)

150

(300)

0110

2.5:1

x2

—

—

100

(200)

125

(250)

150

(300)

166

(333)

187.5

(375)

1000

3:1

x2

—

100

(200)

120

(240)

150

(300)

180

(360)

200

(400)

225

(450)

1110

3.5:1

x2

—

116.6

(233)

140

(280)

175

(350)

210

(420)

233

(466)

—

1010

4:1

x2

100

(200)

133

(267)

160

(320)

200

(400)

——

—

1011

5:1

x2

125

(250)

166.5

(333)

200

(400)

——

—

—

1101

6:1

x2

150

(300)

200

(400)

——

—

—

—

0011

PLL bypass

1111

Clock off

Notes:

1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see

Section 1.4.2.2, “Input AC Specifications,” for valid SYSCLK and VCO frequencies.

2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled,

and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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