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PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

— Tracks unresolved branches and flushes executed, dispatched, and fetched instructions if branch

is mispredicted

— Retires as many as four instructions per clock

•

Separate on-chip instruction and data caches (Harvard architecture)

— 32-Kbyte, four-way set-associative instruction and data caches

— LRU replacement algorithm

— 32-byte (eight-word) cache block size

— Physically indexed/physical tags (Note that the PowerPC architecture refers to physical address

space as real address space.)

— Cache write-back or write-through operation programmable on a per page or per block basis

— Instruction cache can provide four instructions per clock; data cache can provide two words per

clock

— Caches can be disabled in software

— Caches can be locked

— Parity checking performed on both caches

— Data cache coherency (MESI) maintained in hardware

— Secondary data cache support provided

— Instruction cache coherency maintained in software

— Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache

block was made available to the requesting unit at the time it was burst into the line-fill buffer.

Subsequent data was unavailable until the cache block was filled. On the 604e, subsequent data

is also made available as it arrives in the line-fill buffer.

•

Separate memory management units (MMUs) for instructions and data

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— Both TLBs are 128-entry and two-way set associative

— TLBs are hardware reloadable (that is, the page table search is performed in hardware)

— Separate IBATs and DBATs (four each) also defined as SPRs

— Separate instruction and data translation lookaside buffers (TLBs)

— LRU replacement algorithm

— 52-bit virtual address; 32-bit physical address

•

Bus interface features

— Selectable processor-to-bus clock frequency ratios of 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 5:1, and 6:1

— A 64-bit split-transaction external data bus with burst transfers

— Support for address pipelining and limited out-of-order bus transactions

— Four burst write queues—three for cache copyback operations and one for snoop push

operations

— Two single-beat write queues

— Additional signals and signal redefinition for direct-store operations

— Provides a data streaming mode that allows consecutive burst read data transfers to occur

without intervening dead cycles. This mode also disables data retry operations.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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