Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

X28HT010 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # X28HT010
Description  5V, Byte Alterable EEPROM
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

X28HT010 Datasheet(HTML) 3 Page - Renesas Technology Corp

  X28HT010 Datasheet HTML 1Page - Renesas Technology Corp X28HT010 Datasheet HTML 2Page - Renesas Technology Corp X28HT010 Datasheet HTML 3Page - Renesas Technology Corp X28HT010 Datasheet HTML 4Page - Renesas Technology Corp X28HT010 Datasheet HTML 5Page - Renesas Technology Corp X28HT010 Datasheet HTML 6Page - Renesas Technology Corp X28HT010 Datasheet HTML 7Page - Renesas Technology Corp X28HT010 Datasheet HTML 8Page - Renesas Technology Corp X28HT010 Datasheet HTML 9Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 20 page
background image
X28C010, X28HT010
FN8105 Rev 1.00
Page 3 of 20
February 12, 2007
Block Diagram
Pin Descriptions
Addresses (A0-A16)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers, and
is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C010/X28HT010
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010/X28HT010.
Back Bias Voltage (VBB) (X28HT010 only)
It is required to provide -3V on pin 1. This negative voltage
improves higher temperature functionality.
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in a
high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW
and OE is HIGH. The X28C010/X28HT010 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs last.
Similarly, the data is latched internally by the rising edge of
either CE or WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion,
typically within 5ms.
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Decoder
Control
Logic and
Timing
1Mbit
EEPROM
Array
I/O0-I/O7
Data Inputs/Outputs
CE
OE
VCC
VSS
WE
A0-A7
Latches and
A8-A16
Pin Names
SYMBOL
DESCRIPTION
A0-A16
Address Inputs
I/O0-I/O7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
VCC
+5V
VSS
Ground
NC
No Connect
VBB*-3V
*VBB applies to X28HT010 only.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com