MC68331 datasheet(17/32 Pages) NXP

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MC68L300EC16/D

Figure 13 BDM Serial Communication Timing Diagram

Figure 14 BDM Freeze Assertion Timing Diagram

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

Table 7 Background Debugging Mode Timing

and V

DDSYN

= 3.0 to 3.6Vdc, V

= 0 Vdc, T

= T

to T

Num

Characteristic

Symbol

Min

Max

Unit

DSI Input Setup Time

tDSISU

—

DSI Input Hold Time

tDSIH

—

DSCLK Setup Time

tDSCSU

—

DSCLK Hold Time

tDSCH

—

DSO Delay Time

tDSOD

—25

DSCLK Cycle Time

tDSCCYC

2—

tcyc

CLKOUT Low to FREEZE Asserted/Negated

tFRZAN

—50

CLKOUT High to IFETCH High Impedance

tIPZ

—50

CLKOUT High to IFETCH Valid

tIP

—50

DSCLK Low Time

tDSCLO

1—

tcyc

68300 BKGD DBM SER COM TIM

CLKOUT

FREEZE

BKPT/DSCLK

IFETCH/DSI

IPIPE/DSO

68300 BDM FRZ TIM

CLKOUT

FREEZE

IFETCH/DSI

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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