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ICS853S031I Datasheet(PDF) 10 Page - Renesas Technology Corp

Part # ICS853S031I
Description  Low Skew, 1-to-9, Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer
PDF  23 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS853S031I Datasheet(HTML) 10 Page - Renesas Technology Corp

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ICS853S031I Data Sheet
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S031BYI REVISION A AUGUST 17, 2011
10
©2011 Integrated Device Technology, Inc.
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3E. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 3D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 3F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
PCLK
nPCLK
LVPECL
Input
CML
3.3V
Zo = 50
Ω
Zo = 50
Ω
3.3V
3.3V
R1
50
Ω
R2
50
Ω
R3
125
Ω
R4
125
Ω
R1
84
Ω
R2
84
Ω
3.3V
Zo = 50
Ω
Zo = 50
Ω
PCLK
nPCLK
3.3V
3.3V
LVPECL
LVPECL
Input
PCLK
nPCLK
LVPECL
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
Ω
R2
120
Ω
R3
120
Ω
R4
120
Ω
3.3V
R1
100
Ω
CML Built-In Pullup
PCLK
nPCLK
3.3V
LVPECL
Input
Zo = 50
Ω
Zo = 50
Ω
R3
84
R4
84
R1
125
R2
125
R5
100 - 200
R6
100 - 200
PCLK
nPCLK
3.3V LVPECL
3.3V
Zo = 50
Ω
Zo = 50
Ω
3.3V
3.3V
LVPECL
Input
C1
C2
3.3V
R1
100
Ω
LVDS
PCLK
nPCLK
3.3V
LVPECL
Input
Zo = 50
Ω
Zo = 50
Ω



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