TMPR4955AF datasheet(127/168 Pages) TOSHIBA

127 / 168 page

Chapter 6 TX4955A System Interface

6-55

EOD

Data

Write

Addr

Addr1

Addr0

SysAD

SCycle

SClock

SysCmd

EReq*

EValid*

EOK*

PValid*

PMaster*

Figure 6.3.29 Consecutive Processor Write Requests Followed By External Write Request

Block Read Maximum Rate

Maximum block reads can occur with the following data rate:

AxD...DxAxD...D (1 cycle between D and A)

where A

A is the address, D

D is data (four words, or DDDD, in the data cache miss, and 8

words, or DDDDDDDD, in an instruction cache miss), and xxxx is an idle cycle.

Back-to-Back Instruction Cache Misses

With a PClock to SClock ratio of 2:1, back-to-back instruction cache misses can be refilled

with the following data rate:

AxDDDDDDDDxxxAxDDDDDDDD (3 cycles between D and A)

That is, the address is followed by an idle cycle, the instruction is executed, three idle

cycles occur, followed by the next address. This pattern is valid for the case in which two

sequential instructions miss in the instruction cache, each instruction residing on a

different cache line.

Running completely in uncached space (every instruction is uncached and a cache miss)

results in a similar data pattern:

AxDxxxAxD (3 cycles between D and A)

Back-to-Back Uncached Loads

With a PClock to SClock ratio of 2:1, back-to-back uncached doubleword loads have the

following data rate:

AxDDxxxAxDD (3 cycles between D and A)

That is, the address is followed by an idle cycle, a doubleword of data, three idle cycles,

and the next address.

Back-to-back uncached word loads have the following data rate:

AxDxxxAxD (3 cycles between D and A)

TMPR4955AF Datasheet(PDF) 127 Page - Toshiba Semiconductor

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