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S71GS256 Datasheet(PDF) 92 Page - SPANSION |
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S71GS256 Datasheet(HTML) 92 Page - SPANSION |
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92 / 195 page ![]() 92 S29GLxxxN MirrorBitTM Flash Family S29GLxxxN_MCP_A1 December 15, 2004 Advan ce In form ati o n AC Characteristics Read-Only Operations–S29GL128N, S29GL256N, S29GL512N Notes: 1. Not 100% tested. 2. CE#, OE# = VIL 3. OE# = VIL 4. See Figure 9 and Table 14 for test specifications. 5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V. Parameter Description Test Setup Speed Options JEDEC Std. 90 100 110 110 Unit tAVAV tRC Read Cycle Time VIO = VCC = 3 V Min 90 100 110 ns VIO = 1.8 V, VCC = 3 V 110 tAVQV tACC Address to Output Delay (Note 2) VIO = VCC = 3 V Max 90 100 110 ns VIO = 1.8 V, VCC = 3 V 110 tELQV tCE Chip Enable to Output Delay (Note 3) VIO = VCC = 3 V Max 90 100 110 ns VIO = 1.8 V, VCC = 3 V 110 tPACC Page Access Time Max 25 25 25 30 ns tGLQV tOE Output Enable to Output Delay Max 25 25 35 35 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tCEH Chip Enable Hold Time Read Min 35 ns |
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