Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

ADV7392EBZ Datasheet(PDF) 29 Page - Analog Devices

Part # ADV7392EBZ
Description  Low Power, Chip Scale 10-Bit SD/HD Video Encoder
PDF  96 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7392EBZ Datasheet(HTML) 29 Page - Analog Devices

Back Button ADV7392EBZ Datasheet HTML 25Page - Analog Devices ADV7392EBZ Datasheet HTML 26Page - Analog Devices ADV7392EBZ Datasheet HTML 27Page - Analog Devices ADV7392EBZ Datasheet HTML 28Page - Analog Devices ADV7392EBZ Datasheet HTML 29Page - Analog Devices ADV7392EBZ Datasheet HTML 30Page - Analog Devices ADV7392EBZ Datasheet HTML 31Page - Analog Devices ADV7392EBZ Datasheet HTML 32Page - Analog Devices ADV7392EBZ Datasheet HTML 33Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 96 page
background image
ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 29 of 96
Table 17. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0
Pixel data valid off
0x00
ED/HD Pixel Data Valid.
1
Pixel data valid on
0
4×
HD Oversample Rate Select.
1
2×
0
HD test pattern off
ED/HD Test Pattern Enable.
1
HD test pattern on
0
Hatch
ED/HD Test Pattern Hatch/Field.
1
Field/frame
0
Disabled
ED/HD Vertical Blanking Interval (VBI)
Open.
1
Enabled
0
0
Disabled
0
1
−11 IRE
1
0
−6 IRE
ED/HD Undershoot Limiter.
1
1
−1.5 IRE
0
Disabled
0x31
ED/HD Mode
Register 2
ED/HD Sharpness Filter.
1
Enabled
0
0
0
0 clock cycles
0x00
0
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
1
3 clock cycles
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
1
0
0
4 clock cycles
0
0
0
0 clock cycles
0
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
1
3 clock cycles
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
1
0
0
4 clock cycles
0
Disabled
ED/HD CGMS Enable.
1
Enabled
0
Disabled
0x32
ED/HD Mode
Register 3
ED/HD CGMS CRC Enable.
1
Enabled
0
Cb after falling edge of HSYNC
0x68
ED/HD Cr/Cb Sequence.
1
Cr after falling edge of HSYNC
Reserved.
0
0 must be written to this bit
0
8-bit input
ED/HD Input Format.
1
10-bit input1
0
Disabled
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
1
Enabled
Reserved.
0
0 must be written to this bit
0
Disabled
ED/HD Chroma SSAF Filter.
1
Enabled
Reserved.
1
1 must be written to this bit
0
Disable
0x33
ED/HD Mode
Register 4
ED/HD Double Buffering.
1
Enabled
1 Available on the ADV7392/ADV7393 (40-pin devices) only.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com