ICS85214

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

IDT™ / ICS™ HSTL FANOUT BUFFER

7

ICS85214AG

REV. B

JUNE 3, 2016

Parameter Measurement Information, continued

Output Rise/Fall Time

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and

R2/R1 = 0.609.

Figure 2. Single-Ended Signal Driving Differential Input

Clock

Outputs

20%

80%

80%

20%

tR

t F

VSWING

R2

1K

VDD

CLK_IN

R1

1K

C1

0.1uF

V_REF

CLKx

nCLKx