ICS87004AGI REVISION D JANUARY 4, 2010

8

©2009 Integrated Device Technology, Inc.

ICS87004I Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Parameter Measurement Information

3.3V Output Load AC Test Circuit

Differential Input Level

Cycle-to-Cycle Jitter

2.5V Output Load AC Test Circuit

Output Skew

Phase Jitter and Static Phase Offset

SCOPE

Qx

LVCMOS

GND

VDDA,

VDDO

VDD,

1.65V±5%

-1.65V±5%

nCLK[0:1]

CLK[0:1]

VDD

GND

V

CMR

Cross Points

V

PP

Q[0:3]

➤

➤

V

DDO

2

V

DDO

2

V

DDO

2

tcycle n

tcycle n+1

tjit(cc) =

|tcycle n – tcycle n+1|

1000 Cycles

SCOPE

Qx

LVCMOS

GND

1.25V±5%

-1.25V±5%

VDD,

VDDA,

VDDO

Qx

Qy

tsk(o)

V

DDO

2

V

DDO

2

nCLK[0:1]

CLK[0:1]

FB_IN

➤ t(Ø)

V

OH

V

OL

V

OH

V

OL

V

DDO

2

t(Ø) mean = Static Phase Offset

Where t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on the controlled edges.