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S75WS256NDFBAWMA Datasheet(PDF) 71 Page - SPANSION |
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S75WS256NDFBAWMA Datasheet(HTML) 71 Page - SPANSION |
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71 / 216 page  February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 69 Advance Information 12.8 AC Characteristics 12.8.1 CLK Characterization Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Figure 12.6 CLK Characterization 12.8.2 Synchronous/Burst Read Notes: 1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. 3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description 54 MHz 66 MHz 80 MHz Unit fCLK CLK Frequency Max 54 66 80 MHz tCLK CLK Period Min 18.5 15.1 12.5 ns tCH CLK High Time Min 7.4 6.1 5.0 ns tCL CLK Low Time tCR CLK Rise Time Max 3 3 2.5 ns tCF CLK Fall Time Parameter Description 54 MHz 66 MHz 80 MHz Unit JEDEC Standard tIACC Latency Max 80 ns tBACC Burst Access Time Valid Clock to Output Delay Max 13.5 11.2 9 ns tACS Address Setup Time to CLK (Note 1)Min 5 4 ns tACH Address Hold Time from CLK (Note 1)Min 7 6 ns tBDH Data Hold Time from Next Clock Cycle Min 4 3 ns tCR Chip Enable to RDY Valid Max 13.5 11.2 9 ns tOE Output Enable to Output Valid Max 13.5 11.2 ns tCEZ Chip Enable to High Z (Note 2)Max 10 ns tOEZ Output Enable to High Z (Note 2)Max 10 ns tCES CE# Setup Time to CLK Min 4 ns tRDYS RDY Setup Time to CLK Min 5 4 3.5 ns tRACC Ready Access Time from CLK Max 13.5 11.2 9 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 4 ns tAVD AVD# Pulse Min 8 ns tAOE AVD Low to OE# Low Max 38.4 ns tCLK tCL tCH tCR tCF CLK |
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