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S75WS256NDFBAWMA Datasheet(PDF) 74 Page - SPANSION |
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S75WS256NDFBAWMA Datasheet(HTML) 74 Page - SPANSION |
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74 / 216 page  72 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Ad van c e Inf o rmation Notes: 1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data. Figure 12.10 Linear Burst with RDY Set One Cycle Before Data 12.8.4 AC Characteristics—Asynchronous Read Notes: 1. Not 100% tested. 2. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description 54 MHz 66 MHz 80 MHz Unit JEDEC Standard tCE Access Time from CE# Low Max 80 ns tACC Asynchronous Access Time Max 80 ns tAVDP AVD# Low Time Min 8 ns tAAVDS Address Setup Time to Rising Edge of AVD# Min 4 ns tAAVDH Address Hold Time from Rising Edge of AVD# Min 7 6 ns tOE Output Enable to Output Valid Max 13.5 ns tOEH Output Enable Hold Time Read Min 0 ns Data# Polling Min 10 ns tOEZ Output Enable to High Z (see Note) Max 10 ns tCAS CE# Setup Time to AVD# Min 0 ns Da+1 Da Da+2 Da+3 Da + n OE# Data Addresses Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tAOE tBDH 6 wait cycles for initial access shown. Hi-Z Hi-Z Hi-Z 12 3 4 5 6 tRDYS tBACC tCR |
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