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S75WS256NDFBAWMA Datasheet(PDF) 81 Page - SPANSION |
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S75WS256NDFBAWMA Datasheet(HTML) 81 Page - SPANSION |
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81 / 216 page  February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 79 Advance Information Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, . 3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before data. Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6 Figure 12.20 DQ2 vs. DQ6 CE# CLK AVD# Addresses OE# Data RDY Status Data Status Data VA VA tIACC tIACC Enter Erase Erase Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase WE# DQ6 DQ2 Erase Complete Erase Suspend Suspend Program Resume Embedded Erasing |
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