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S75WS256NDFBAWMA Datasheet(PDF) 97 Page - SPANSION

Part # S75WS256NDFBAWMA
Description  Stacked Multi-Chip Product (MCP)
PDF  216 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S75WS256NDFBAWMA Datasheet(HTML) 97 Page - SPANSION

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Publication Number S75WS-N-00
Revision A Amendment 0 Issue Date February 17, 2005
DATA SHEET
S29RS512N
512 Megabit (32 M x 16-Bit) CMOS 1.8 Volt-only
Read/Write, Burst Mode, Mass Storage Flash Memory
for Multi-Chip Products (MCP)
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65
to 1.95 volt)
Manufactured on 0.11 µm MirrorBitTM process
Read/Write operation
— Zero latency between read and write operations
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with or without
wrap-around
— Continuous Sequential Burst
Sector Architecture
— one-hundred-twenty-eight 256 Kword sectors
100,000 erase cycle per sector typical
20-year data retention typical
Performance Charcteristics
Read access times at 80/66/54 MHz
— Burst access times of 9.1/11.2/13.5 ns
— Synchronous latency of 148 ns
— Asynchronous random access times of 143 ns
High Performance
— Typical word programming time of 40 µs
— Typical effective word programming time of 9.4 µs
utilizing a 32-Word Write Buffer at Vcc Level
— Typical effective word programming time of 6 µs
utilizing a 32-Word Write Buffer at ACC Level
— Typical 2 s sector erase time for 256 Kword sectors
Power dissipation (typical values, CL = 30 pF)
@ 80 MHz
— Continuous Burst Mode Read: 35 mA
— Program: 19 mA
—Erase: 19 mA
— Standby mode: 20 µA
Hardware Features
Sector Protection
— Dynamic Protection Bits (DYB) are assigned to every
sector
— A command sector protection to lock/unlock
combinations of individual sectors to prevent/allow
program or erase operations within that sector.
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
ACC input: Acceleration function reduces
programming time in a factory setting
Low VCC write inhibit
Software Features
Software command set compatible with
JEDEC 42.4 standards
Data# Polling and toggle bits
— Provides a software method of detecting program and
erase operation completion
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Program Suspend/Resume
— Suspends a programming operation to read data from
a sector other than the one being programmed, then
resume the programming operation
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Additional Features
Program Operation
— Ability to perform synchronous and asynchronous
write operation independent of burst control register
setting



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