a e- i

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IT bl B

Table2

PCI STOP# SMBus Contro

vteO e· 3

PCI_STOP#

Byte O Bit 3

Byte 0, Bit 3 Read Bit

(Pin 30)

Write Bit

(Internal Status)

0

0

0

0

1

0

1

0

0

1

1

1'

Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.

Table3

CPUCLKT/C (1:0) Outputs SMBus Control Table

CPU_STOP#

Byte 1

CPUCLKT/C (1:0) Outputs

(Pin 45\

Bit 4. 5

0

0

Stop

0

1

Running

1

0

Running

1

1

Running

Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 4, and 5.

Table4

PCICLK F (2:0 Outputs SMBus ControlTable

PCI_STOP#

Byte 3

PCICLK (2:0) Outputs

lPin 30\

Bit 3 4 5

0

0

Stop

0

1

Running

1

0

Running

1

1

Running

Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.

Table5

3V66 (4:2) SMBus Control Table

CPU_STOP#

Byte 5

3V66 (4:2)

(Pin 45)

Bit 5

0

0

Running

0

1

Stopped

1

0

Running

1

1

Running

Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 17, 18, and 19

Table6

3V66 (1) SMBus ControlTable

CPU_STOP#

Byte 5

3V66 (1)

(Pin 45)

Bit 4

0

0

Running

0

1

Stopped

1

0

Running

1

1

Running

Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 31.

0825F-11/19/03

10

ICS950818