ICS950818

PCI_STOP# - Assertion (transition from logic "1" to logic "O")

The impact of asserting the PCI_STOP# signal will be the following. All PCl[10:0] and stoppable PCI_F clocks will latch

low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the

next rising edge.

Assertion of PCI_STOP# Waveforms

PCI_STOP# 1------.

------------------------

PC1_F 33MHz

PCI 33MHz

CPU_STOP# - Assertion (transition from logic "1" to logic "O")

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the SMBus configuration to be stoppable

via assertion of CPU_STOP# are to be stopped after their next transition. When the SMBus Bit 6 of Byte 1 is

programmed to 'O' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change

to the output drive current values. The CPU will be driven high with a current value equal to (Mult O 'select') x (Iref), the

CPU# signal will not be driven . When the SMBus Bit 6 of Byte 1 is programmed to '1' then final state of the stopped

CPU signals is Low, both CPU and CPU# outputs will not be driven.

Assertion of CPU_STOP# Waveforms

CPUCLKT

CPU_STOP#

�

CPUCLKC

'-----------------

CPU_STOP# Functionality

CPU_STOP#

CPUT

CPUC

1

Normal

Normal

0

iref * Mult

Float

G

t

G

roup o roup SkewsatCommon T

"f

rans, 10n Ed1ges: n u ere

o e

Ubff dMd

GROUP

SYMBOL

CONDITIONS

MIN

TYP

3V66 to PCl1 •2

S3V66-PCI

3V66 (4:1) leads 33MHz PCI

1.5

2.765

1Guaranteed by design, not 100% tested in production.

2

500ps Tolerance

0825F-11/19/03

16

MAX

3.5

UNITS

ns