16

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

NOTES:

1. RS1 must be HIGH during Partial Reset.

2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 4. Partial Reset (IDT Standard and FWFT Modes)

NOTES:

1. PRS must be HIGH during Reset.

2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)

tRSF

CLKA

RS1, RS2

FF/IR

AE

AF

MBF1,

MBF2

CLKB

EF/OR

FS2,

FS1,FS0

5610 drw05

tRSTS

tRSTH

tFSH

tFSS

tWFF

tREF(2)

tRSF

0,1

tRSF

BE

BE/

FWFT

FWFT

tBES

1

2

tFWS

tBEH

tWFF

RTM

LOW

CLKA

PRS

FF/IR

AE

AF

MBF1,

CLKB

EF/OR

5610 drw 06

tRSTS

tRSTH

tWFF

tWFF

tREF

tRSF

tRSF

tRSF

MBF2

(2)

RTM

LOW