MC68340 datasheet(118/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

4- 21

NOTE

An access to this register does not affect external space since

the cycle is not run externally.

Example code for accessing the MBAR is as follows:

MOVE.L

#7,D0

load D0 with the CPU space function code

MOVEC.L

D0,SFC

load SFC to indicate CPU space

LEA.L

$0003FF00,A0

load A0 with the address of MBAR

MOVES.L

(A0),D0

load D0 with the contents of MBAR

Address $0003FF00 in CPU space (MBAR) will be loaded with the value $FFFFF001.

This value will set the base address of the internal registers to $FFFFF. MBAR can be

written to using the following code:

MOVE.L

#7,D0

load D0 with the CPU space function code

MOVEC.L

D0,DFC

load DFC to indicate CPU space

LEA.L

$0003FF00,A0

load A0 with the address of MBAR

MOVE.L

#$FFFFF001,D0

load D0 with the value to be written into MBAR

MOVES.L

D0,(A0)

write the value contained in D0 into MBAR

4.3.2 System Configuration and Protection Registers

The following paragraphs provide descriptions of the system configuration and protection

registers.

4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the

SIM40 configuration, can be read or written at any time.

MCR

$000

9876543210

FRZ1

FRZ0

FIRQ

SHEN1

SHEN0

SUPV

IARB3

IARB2

IARB1

IARB0

RESET:

0110000010001111

Supervisor Only

Bits 15, 11, 10, 6–4—Reserved

FRZ1—Freeze Software Enable

1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer

counters are disabled, preventing interrupts from occurring during software

debug.

0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer

counters continue to run. See 4.2.7 Freeze for more information.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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