MC68340 datasheet(187/441 Pages) FREESCALE

187 / 441 page

5- 50

MC68340 USER’S MANUAL

MOTOROLA

If an instruction is executed and an interrupt is pending on completion, the trace exception

is processed before the interrupt exception.

If an instruction forces an exception, the forced exception is processed before the trace

exception.

If an instruction is executed and a breakpoint is pending upon completion of the

instruction, the trace exception is processed before the breakpoint.

If an attempt is made to execute an illegal, unimplemented, or privileged instruction while

tracing is enabled, no trace exception will occur because the instruction is not executed.

This is particularly important to an emulation routine that performs an instruction function,

adjusts the stacked PC to beyond the unimplemented instruction, and then returns. The

SR on the stack must be checked to determine if tracing is on before the return is

executed. If tracing is on, trace exception processing must be emulated so that the trace

exception handler can account for the emulated instruction.

Tracing also affects normal operation of the STOP and LPSTOP instructions. If either

instruction begins execution with T1 set, a trace exception will be taken after the

instruction loads the SR. Upon return from the trace handler routine, execution will

continue with the instruction following STOP (LPSTOP), and the processor will not enter

the stopped condition.

5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable

interrupt vectors within each exception vector table. Careful use of multiple vector tables

and hardware chaining will permit a virtually unlimited number of peripherals to interrupt

the processor.

Interrupt recognition and subsequent processing are based on internal interrupt request

signals (

IRQ7–IRQ1) and the current priority set in SR priority mask I2–I0. Interrupt

request level zero (

IRQ7–IRQ1 negated) indicates that no service is requested. When an

interrupt of level one through six is requested via

IRQ6– IRQ1, the processor compares

the request level with the interrupt mask to determine whether the interrupt should be

processed. Interrupt requests are inhibited for all priority levels less than or equal to the

current priority. Level seven interrupts are nonmaskable.

IRQ7–IRQ1 are synchronized and debounced by input circuitry on consecutive rising

edges of the processor clock. To be valid, an interrupt request must be held constant for

at least two consecutive clock periods.

Interrupt requests do not force immediate exception processing, but are left pending. A

pending interrupt is detected between instructions or at the end of exception processing—

all interrupt requests must be held asserted until they are acknowledged by the CPU. If

the priority of the interrupt is greater than the current priority level, exception processing

begins.

Exception processing occurs as follows. First, the processor makes an internal copy of the

SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is

set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 Datasheet(PDF) 187 Page - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 187 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL