MC68340 datasheet(192/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 55

The SSW for a released write fault contains the following bit pattern:

98765432

000

1000

SIZ

FUNC

TR, B1, and B0 are set if the corresponding exception is pending when the bus error

exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and

FUNC fields.

The remainder of the stack contains the PC of the next unexecuted instruction, the current

SR, the address of the faulted memory location, and the contents of the data buffer that

was to be written to memory. This data is written on the stack in the format depicted in

Figure 5-15. When a released write fault exception handler executes, the machine will

complete the faulted write and then continue executing instructions wherever the PC

indicates.

5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus

error exceptions are included in this category—all instruction prefetches, all operand

reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP

(except the last write of a MOVEP Rn,

〈ea〉 or the last write of MOVEM, which are type I

faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not

considered released.

All type II faults cause an immediate exception that aborts the current instruction. Any

registers that were altered as the result of an EA calculation (i.e., postincrement or

predecrement) are restored prior to processing the bus cycle fault.

The SSW for faults in this category contains the following bit pattern:

98765432

0000

SIZ

FUNC

The trace pending bit is always cleared, since the instruction will be restarted upon return

from the handler. Saving a pending exception on the stack causes a trace exception to be

taken prior to restarting the instruction. If the exception handler does not alter the stacked

SR trace bits, the trace is requeued when the instruction is started.

The breakpoint pending bits are stacked in the SSW, even though the instruction is

restarted upon return from the handler. This avoids problems with bus state analyzer

equipment that has been programmed to breakpoint only the first access to a specific

location or to count accesses to that location. If this response is not desired, the exception

handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ fields all

reflect the type of bus cycle that caused the fault. If the bus cycle was an RMW, the RM bit

will be set, and the RW bit will show whether the fault was on a read or write.

Freescale Semiconductor, Inc.

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