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DP83849IF Datasheet(PDF) 67 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DP83849IF
Description  PHYTER짰 DUAL Industrial Temperature with Fiber Support (FX) an Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver
PDF  108 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83849IF Datasheet(HTML) 67 Page - National Semiconductor (TI)

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7.1.13 Page Select Register (PAGESEL)
This register is used to enable access to the Link Diagnostics Registers.
11
DUP_INT
0, RO/COR
Change of duplex status interrupt:
1 = Duplex status change interrupt is pending and is cleared by
the current read.
0 = No duplex status change interrupt pending.
10
ANC_INT
0, RO/COR
Auto-Negotiation Complete interrupt:
1 = Auto-negotiation complete interrupt is pending and is cleared
by the current read.
0 = No Auto-negotiation complete interrupt pending.
9
FHF_INT
0, RO/COR
False Carrier Counter half-full interrupt:
1 = False carrier counter half-full interrupt is pending and is
cleared by the current read.
0 = No false carrier counter half-full interrupt pending.
8
RHF_INT
0, RO/COR
Receive Error Counter half-full interrupt:
1 = Receive error counter half-full interrupt is pending and is
cleared by the current read.
0 = No receive error carrier counter half-full interrupt pending.
7
LQ_INT_EN
0, RW
Enable Interrupt on Link Quality Monitor event
6
ED_INT_EN
0, RW
Enable Interrupt on energy detect event
5
LINK_INT_EN
0, RW
Enable Interrupt on change of link status
4
SPD_INT_EN
0, RW
Enable Interrupt on change of speed status
3
DUP_INT_EN
0, RW
Enable Interrupt on change of duplex status
2
ANC_INT_EN
0, RW
Enable Interrupt on Auto-negotiation complete event
1
FHF_INT_EN
0, RW
Enable Interrupt on False Carrier Counter Register half-full event
0
RHF_INT_EN
0, RW
Enable Interrupt on Receive Error Counter Register half-full event
Table 32. Page Select Register (PAGESEL), address 13h
Bit
Bit Name
Default
Description
15:2
RESERVED
0, RO
RESERVED: Writes ignored, Read as 0
1:0
PAGE_SEL
0, RW
Page_Sel Bit:
Selects between paged registers for address 14h to 1Fh.
0 = Extended Registers Page 0
1 = RESERVED
2 = Link Diagnostics Registers Page 2
Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h



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