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DS20005853E-page 13

MIC4605

5.0

BLOCK DIAGRAM

For HO to be high, HI must be high and LO must be low. HO going high is delayed by LO falling below 1.9V. The HI and

LI inputs must not rise at the same time to prevent a glitch from occurring on the output. A minimum 50 ns delay between

both inputs is recommended.

LO is turned off very quickly on the LI falling edge. LO going high is delayed by the longer of a 35 ns delay of the HO

control signal going “off” or the RS latch being set.

The latch is set by the quicker of either the falling edge of HS or the LI gated delay of 240 ns. The latch is present to

lockout LO bounce due to ringing on HS. If HS never adequately falls due to the absence of or the presence of a very

weak external pull-down on HS, the gated delay of 240 ns at LI will set the latch, allowing LO to transition high. This, in

turn, allows the LI start-up pulse to charge the bootstrap capacitor if the load inductor current is very low and HS is

uncontrolled. The latch is reset by the LI falling edge.

FIGURE 5-1:

MIC4605 Top-Level Block Diagram.

FIGURE 5-2:

MIC4605-1 Cross-Conduction Lockout/PWM Input Logic Block Diagram.

V

DD

UVLO

HB

UVLO

LEVEL

SHIFT

INPUT LOGIC

(SEE BLOCK

DIAGRAM)

S

_

R

Q

–2 ONLY

–1 HI

–2 PWM

V

DD

EN

HB

HO

HS

LO

OR

EDGE

V

SS

V

IN

–1 ONLY

–1 LI

–2 NC

BIAS

RELIEF

2.2V

HS

LI

LO

HI

HO SECTION

AND INPUT

LO SECTION

FF RESET

35 ns

DELAY

Q

R

S

240 ns

DELAY

1.9V